Integrated circuits generally include a plurality of circuit elements which have to be electrically insulated from each other. Some active components that are part of integrated circuits, for instance, Bipolar and DMOS transistors, use a heavily-doped buried layer as collector or drain region.
Present Smart Power Technology (SPT) products combine Bipolar, CMOS and DMOS circuit elements (also named as BCD technologies) on one chip. High requirements on the electrical strength, the current carrying capacity and the turn-on resistance Ron are made. The insulation of separate circuit elements from each other has to have a high breakdown voltage UBD. A homogeneous power distribution and a small turn-on resistance Ron are important parameters for the contacts to the buried layer and to the substrate. At the same time, the insulation and the contact to the buried layer and to the substrate should be realized on a small surface area of the circuit.
At the beginning, the insulation and the contact to the buried layer and to the substrate were realized by diffusion regions which take up a large surface area and increase the thermal budget through the necessary temperatures during the formation process causing not-wanted diffusion processes into other layers.
The insulation and partly also the contact to the buried layer may be realized by etching trenches.